As electronic devices increase in complexity, data transfer and processing within these devices require greater coordination. One method to coordinate the data transfer and processing in these devices involves clocking. Numerous clocking schemes exist.
In derived clock systems, a remote receiving agent recovers and tracks clock phase information embedded in an incoming data stream. A tracking loop in the receiver may perform this function. Tracking loops should align to the data stream clocking prior to data reception (to account for clock phase skew between transmitter and receiver) and at regular intervals during transmission to correct for drift in a communication link. Drift and other clocking maladies can arise from fluctuations in voltage, temperature, manufacturing variations or other causes.
Conventional tracking loops examine multiple samples of an incoming data stream to determine which direction to shift a local clock to align with the center of an incoming data-eye. A system that extracts two samples per incoming data bit is shown in FIG. 1. Additionally, FIG. 1 illustrates two consecutive data bits at a receiver. Ideally, for proper capture of the incoming data stream, it is desirable to align consecutive sampling clock edges at the center and at the edge locations of a data eye. Thus, ri and rib should ideally be at the center of the data eye 1 or data eye 2 and rq and rqb at edge locations. A local clock is aligned by comparing edge samples with data samples on either side and inferring whether the edge occurred early or late and advancing or retarding the local clock to align to the remote sending clock.
FIG. 2 illustrates a voting process in a derived clock system. Referring to FIG. 2, votes are generated at data transitions, based on edge location. The dashed transition lines indicate two possible scenarios for edge alignment with respect to the sampler capturing the edge value. Generally, only these extreme scenarios are of significance since metastable values will resolve into a 1 or a 0 at the output of the receiver.
The receiver may align to the incoming data stream clock based on edge alignment. An edge falling along the large dashed line will sample a value coinciding with the latter of the two bits comprising a transition. An edge following the small dashed line samples a value coinciding with the former of the two bits. The local clock therefore may shift to the desired center, thus, a large dashed line edge will cause a retard vote and a small dashed line edge an advance vote.
Votes may be filtered for system stability. Once votes in a particular direction are above a filter threshold, the local clock is shifted in the desired direction. In an ideal system, once aligned to the center of the data eye, the number of advance and retard votes will statistically be equal, and therefore not exceed the filter threshold.
To simplify design of an analog front end, it is typical to employ a 1:2 or 1:4 de-multiplexed scheme between the receiver and its core. A high sampling rate can therefore be achieved without having any of the circuits run at full-speed. That is, serial to parallel conversion of data into data words is typically performed before any processing of the data.
Furthermore, voting schemes may provide additional accuracy. For example, in a biased voting scheme, specific clock phases are required to align to even or odd bit locations. In this case, referring to FIG. 2, ri will have to align strictly to data eye position #1 (odd position) and rib to data eye position #2 (even position).
Conventional tracking loops use high transition density patterns and various voting schemes to derive clocking information from incoming signals. However, communication is only performed with different patterns after tracking is accomplished.